1. Field of the Invention
This invention relates generally to systems for testing electronic circuits, and more specifically, to a novel Array Build-In Self-Test (ABIST) circuit and methodology for determining bitmaps of circuit defects in embedded microprocessor arrays.
2. Discussion of the Prior Art
Embedded arrays of microprocessors are commonly tested using Array Built-In Self-Test (xe2x80x9cABISTxe2x80x9d). In order to produce a 2-dimensional map of array defects (called a bit-fail map or xe2x80x9cbitmapxe2x80x9d) many ABIST designs include a signal which indicates a fail has been detected on an ABIST cycle. This signal is routed to an external pin on the product (called a real-time pin), and can be monitored by the device tester. In the classic manner of creating bitmaps using such a scheme, the tester creates a list of the failing cycles, and then, in a separate set of ABIST executions, runs the ABIST machine to the failing cycle and performs a latch scan-out of the internal state of the ABIST machine.
The problem with this scheme is that it is very time consuming. Multiple executions of the ABIST machine are necessary to collect the fail data. In many instances, the data is not unique from one device to the next. For example, a catastrophic fail of the array would create a bitmap showing every cell in the array is defective. Thus, it would be highly desirable to provide for an ABIST, a mechanism for creating bitmaps only when they are unique.
Other approaches for addressing the problem of too much test time have involved the collection of partial data, rather than all the data, and assuming that the fail continues (i.e., what appears to be a bitline is a bitline). However, this solution runs the risk of incorrectly identifying the failing mechanism (i.e., a partial bitline rather than a full bitline fail). In addition, even though this technique reduces the number of ABIST executions, it still requires multiple reruns which collect non-unique data.
It would thus additionally be highly desirable to provide for an ABIST, a mechanism for eliminating extra data collection executions in the determination of bitmaps.
It is an object of the present invention to provide an Array Built-in Self-test (ABIST) system and methodology for testing embedded electronic circuits having a mechanism for creating bitmaps of failures only when they are unique.
It is another object of the present invention to provide an Array Built-in Self-test (ABIST) system and methodology for testing embedded electronic circuits having a mechanism for eliminating extra data collection executions in the determination of bitmaps for locating circuit defects.
According to the invention, there is provided a built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether said generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.
For this scheme to work, a table of signatures would have to be created. This can be done by creating a bitmap for those devices which exhibit what is suspected to be a common failing mode, as well as the associated signature from the real-time fail pin.
Advantageously, such a system and method of the invention conserves test time through the elimination of extraneous data collection by creating a signature at the same time that the initial ABIST execution is performed so that extra data collection executions in the determination of bitmaps may be eliminated.